1. Field of the Invention
This invention generally relates to semiconductor processing and, more specifically, to the formation of interconnects within substrates for making underside contact to source and drain regions of field effect transistors.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
The fabrication of integrated circuits includes the formation of several different metallization structures, including interconnect lines, contacts, and vias, to connect conductive components of a circuit. In particular, contacts and vias are generally used to provide vertical electrical connections between conductive components arranged among different planes of a circuit. In some cases, contacts may refer to metallization structures used to connect a transistor component (e.g., a source or drain region or a gate electrode) with an overlying interconnect line. In contrast, vias may refer to metallization structures used to connect two interconnect lines having an insulating layer interposed therebetween. The terms “contacts” and “vias”, however, may be interchangeably referenced in some cases. In any case, interconnect lines differ from contacts and vias in that they are generally used to provide lateral electrical connections between conductive components arranged along a same plane parallel to a surface of a die substrate. The conductive components directly coupled to the interconnect lines may include contacts and/or vias. In other embodiments, interconnect lines may be formed in direct contact with a conductive element of a field effect transistor, such as a source or drain region or a transistor gate, without the use of a via or a contact and, thus, without an intervening insulating layer. Such interconnect lines do not permit traversal over unrelated conductive regions on the same plane of the die and, consequently, their routing is typically limited to interconnection between adjacent conductive elements and cannot be extended to traverse over several devices. For that reason, such interconnect lines are commonly referred to as “local interconnects.”
In general, circuits are designed such that metallization structures are arranged as wclose as possible to each other and other device components of the circuit to minimize circuit area and die cost without causing circuit faults. In some cases, however, the arrangement of metallization structures may be limited, particularly in regard to components of field effect transistors. In particular, contact structures and local interconnects arranged upon surfaces of source and drain regions induce a parasitic gate-to-contact capacitance. Such a capacitance may limit the switching speed of a transistor, an affect which is expected to become more prevalent as smaller feature dimensions continue to be imposed by advancements in technology. In order to limit the level of such a capacitance, circuits are sometimes designed to have contact structures and/or local interconnects spaced a specific distance from a transistor gate. In conventional designs, such a spacing is generally greater than approximately 70 nm, causing valuable die space to be occupied. In particular, source and drain regions need to be sufficiently large to provide such a spacing as well as room for the contact structures or local interconnects and a margin of error for deviations of alignment when forming the contact structures or local interconnects on the source and drain regions.
In addition or alternative to the arrangement of local interconnects being limited with regard to the location of transistor gates, the restriction of local interconnects over limited regions of a circuit imparts a significant constraint for connecting conductive components within non-adjacent devices at a level near the base of the integrated circuit, forcing many interconnects to be formed at higher levels within a circuit. It is generally recognized, however, that the formation of features within design specifications becomes increasingly more difficult within higher levels of a circuit. In particular, as more levels of a circuit are formed, the planarity of the topography lessens. As a result, problems with step coverage of deposited materials may arise. Furthermore, if a topography is nonplanar, a patterned image may be distorted and the intended structure may not be formed to the specifications of the device.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.